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PIC18F87J11 FAMILY

DS39778E-page 106

2007-2012 Microchip Technology Inc.

8.1

External Memory Bus Control

The operation of the interface is controlled by the

MEMCON register (Register 8-1). This register is

available in all program memory operating modes

except Microcontroller mode. In this mode, the register

is disabled and cannot be written to.

The EBDIS bit (MEMCON<7>) controls the operation

of the bus and related port functions. Clearing EBDIS

enables the interface and disables the I/O functions of

the ports, as well as any other functions multiplexed to

those pins. Setting the bit enables the I/O ports and

other functions, but allows the interface to override

everything else on the pins when an external memory

operation is required. By default, the external bus is

always enabled and disables all other I/O.

The operation of the EBDIS bit is also influenced by the

program memory mode being used. This is discussed

in more detail in Section 8.5 “Program Memory

Modes and the External Memory Bus”

The WAITx bits allow for the addition of Wait states to

external memory operations. The use of these bits is

discussed in Section 8.3 “Wait States”.

The WMx bits select the particular operating mode

used when the bus is operating in 16-Bit Data Width

mode. These are discussed in more detail in

Section 8.6 “16-Bit Data Width Modes”

. These bits

have no effect when an 8-bit Data Width mode is

selected.

The MEMCON register (see Register 8-1) shares the

same memory space as the PR2 register and can be

alternately selected, based on the designation of the

ADSHR

bit

the

WDTCON

(see

REGISTER 8-1:

MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

R/W-0

EBDIS

—WAIT1

WAIT0

—

—WM1

WM0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EBDIS

: External Bus Disable bit

= External bus is enabled when the microcontroller accesses external memory; otherwise, all

external bus drivers are mapped as I/O ports

= External bus is always enabled, I/O ports are disabled

bit 6

Unimplemented

: Read as ‘0’

bit 5-4

WAIT<1:0>:

Table Reads and Writes Bus Cycle Wait Count bits

= Table reads and writes will wait 0 TCY

= Table reads and writes will wait 1 TCY

= Table reads and writes will wait 2 TCY

= Table reads and writes will wait 3 TCY

bit 3-2

Unimplemented

: Read as ‘0’

bit 1-0

WM<1:0>: TBLWT

Operation with 16-Bit Data Bus Width Select bits

= Word Write mode: TABLAT word output, WRH is active when TABLAT is written

= Byte Select mode: TABLAT data is copied on both MSB and LSB, WRH and (UB or LB) will activate

= Byte Write mode: TABLAT data is copied on both MSB and LSB, WRH or WRL will activate

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